All
Search
Images
Videos
Maps
News
More
Shopping
Flights
Travel
Notebook
Report an inappropriate content
Please select one of the options below.
Not Relevant
Offensive
Adult
Child Sexual Abuse
Length
All
Short (less than 5 minutes)
Medium (5-20 minutes)
Long (more than 20 minutes)
Date
All
Past 24 hours
Past week
Past month
Past year
Resolution
All
Lower than 360p
360p or higher
480p or higher
720p or higher
1080p or higher
Source
All
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
Price
All
Free
Paid
Clear filters
SafeSearch:
Moderate
Strict
Moderate (default)
Off
Filter
2:11
CMOS based Voltage Level Shifter Design and Simulation | Cadence
…
1.4K views
6 months ago
YouTube
Success Point for VLSI
1:05
What is Setup Slack in VLSI Design?
1.2K views
2 weeks ago
YouTube
Cadence Design Systems
0:33
2.9K views · 48 reactions | Watch this quick tutorial on how to paint
…
1.3K views
1 week ago
Facebook
Davison Design
2:57
Digital IC Design | VLSI Placement #semiconductor #vlsijobs #vlsisal
…
8K views
7 months ago
YouTube
VLSI POINT
0:14
xcel1ney on TikTok
1.5K views
5 months ago
TikTok
xcel1ney
1:00
TNS Optimization in Cadence Genus | Timing Optimization Techniques
…
138 views
1 month ago
YouTube
Maharshi Sanand Yadav T
0:47
Generate HDL code from Simulink Model #Shorts
848 views
Jul 23, 2022
YouTube
MATLAB Helper ®
3:00
Modern Digital Circuit Design with AI — No Code Needed!
257 views
3 months ago
YouTube
INKOR Technologies Private Limited
2:12
Operators in Verilog HDL | Concatenation & Replication Tutor
…
61 views
1 month ago
YouTube
Chip Logic Studio
1:00
12.What is hold time violation How do you fix it Behavioral
131 views
3 weeks ago
YouTube
Maharshi Sanand Yadav T
0:59
How to interpret your cholesterol panel
204 views
Nov 7, 2024
YouTube
Sean P. Nikravan MD
2:25
Understanding Procedural Blocks – initial, always, final
182 views
1 month ago
YouTube
Chip Logic Studio
1:22
🔧 Verilog MUX Design & Testbench in 60 Seconds! 💻 | Digital Design Basics
215 views
5 months ago
YouTube
Chip Logic Studio
2:59
Verilog Day 1: Introduction and Data Types Explained from Scratch
75 views
2 months ago
YouTube
Chip Logic Studio
1:09
SystemVerilog case vs casex vs casez
171 views
5 months ago
YouTube
Chip Logic Studio
3:00
Operators in Verilog HDL | Concatenation & Replication Tutor
…
1 month ago
YouTube
Chip Logic Studio
0:39
Hold Analysis
223 views
1 month ago
YouTube
Maharshi Sanand Yadav T
0:26
create_clock | example 3 | sdc constraints | synthesis | STA #sta
…
80 views
4 weeks ago
YouTube
Maharshi Sanand Yadav T
1:33
Low HDL Cholesterol Causes explained in 1 minute.
118 views
3 weeks ago
YouTube
Health Zippy
2:58
Verilog Day 1: Introduction and Data Types Explained from Scratch
259 views
1 month ago
YouTube
Chip Logic Studio
0:19
Calling Pins in Footprint | PCB Design Course | Footprints in Alle
…
610 views
Sep 7, 2024
YouTube
LtlBiTech
1:00
Total cholesterol to HDL ratio #prevention #heartdisease #heart
…
1K views
9 months ago
YouTube
Dr. Monali Desai
JIG 2 en Snare Tutorial: Drumline Cadence Performance
255.7K views
Oct 12, 2023
TikTok
renatus1401
0:55
Triglyceride to HDL Ratio — Should You Really Focus on It for Heart H
…
5.9K views
Sep 20, 2024
YouTube
Dr. Mike Hart
0:49
High Quality HDR Video Editing with Just One Click
829.5K views
Nov 20, 2023
TikTok
shiv_gopal_
1:00
Core Electronics Companies | Product-based & Service-based #v
…
199.1K views
Sep 21, 2024
YouTube
VLSI POINT
Sweet Balloon Drawing Tutorial | BFF Artwork Ideas
816K views
Aug 9, 2021
TikTok
thesketchingdoro
0:12
Truyện Hồi Hộp: Hóng Chap Mới của Đam Mỹ
68.5K views
8 months ago
TikTok
_hdl17
Exploring the World of Haidilao: Singapore Edition
1.3M views
Dec 13, 2023
TikTok
gracelsyy
0:12
Understanding Yandere Characters in Literature
65.6K views
11 months ago
TikTok
_hdl17
See more videos
More like this
Feedback